In modern semiconductor device applications; millions of individual devices are packed onto a single small area of a semiconductor substrate, and many of these individual devices may need to be electrically isolated from one another. One method of accomplishing such isolation is to form a trenched isolation region between adjacent devices. Such trenched isolation region will generally comprise a trench or cavity formed within the substrate and filled with an insulative material, such as silicon dioxide.
A prior art method for forming trench isolation regions is described with reference to FIGS. 1–10. Referring to FIG. 1, a semiconductive wafer fragment 10 is shown at a preliminary stage of a prior art processing sequence. Wafer fragment 10 comprises a semiconductive material 12 having an upper surface 13. A layer of silicon dioxide 14 is formed over upper surface 13, and a layer of silicon nitride 16 is formed over silicon dioxide 14. A patterned masking layer 18 is formed over silicon nitride 16.
Substrate 12 can comprise, for example, monocrystalline silicon lightly doped with a conductivity enhancing material. For purposes of interpreting this document and the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Silicon dioxide layer 14 has a typical thickness of about 90 Å, nitride layer 16 has a typical thickness of from about 700 Å to about 800 Å, and masking layer 18 has a typical thickness of about 10,000Å. Nitride layer 16 comprises a lower surface 15 and an upper surface 17. Patterned masking layer 18 can comprise, for example, photoresist.
Referring to FIG. 2, a pattern is transferred from layer 18 to nitride layer 16 and oxide layer 14 to form masking blocks 20 over substrate 12. Blocks 20 are separated by intervening openings (also referred to as trenches or gaps) 22, 24, 26, 28 and 30. Gaps 22, 24, 26, 28 and 30 define locations wherein isolation regions will ultimately be formed. In the shown typical embodiment, gaps 22, 24, 26, 28 and 30 vary in width, with gap 26 representing a wide trench. The variation in width of gaps 22, 24, 26, 28 and 30 is a matter of discretion for persons fabricating devices over substrate 12. Such variation in width is shown to exemplify how particular problems associated with polishing processes (the problems are discussed below) become exaggerated at wider trench openings.
Referring to FIG. 3, openings 22, 24, 26, 28 and 30 are extended into substrate 12. The processing of FIGS. 2 and 3 typically occurs in a single etch step.
Referring to FIG. 4, photoresist material 18 (FIG. 3) is removed. Subsequently, an insulative material 40 is provided to fill the trenches 22, 24, 26, 28 and 30. Insulative material 40 typically comprises silicon dioxide, and can be formed by, for example, high density plasma deposition. The term “high density” as used in this document to refer to a deposition plasma means a deposition plasma having a density of greater than 1010 ions/cm3. The outer surface of the deposited insulative material 40 comprises surface peaks 42 (which actually have a three-dimensional pyramid shape) extending over the patterned nitride material 16. Peaks 42 result as an aspect of high density plasma deposition.
Referring to FIG. 5, wafer fragment 10 is subjected to a polishing process to remove insulative material 40 from over nitride layer 16, and to thereby remove peaks 42 (FIG. 4) and polish the insulative material 40 down to about even with an upper surface of nitride 16. After the polishing process, insulative material 40 forms isolation regions 50, 52, 54, 56 and 58 within openings 22, 24, 26, 28 and 30, respectively. The isolation regions and silicon nitride layer 16 comprise a coextensive upper surface 60. Upper surface 60 can be at about a same elevational level as original upper surface 17 (FIG. 1) of nitride layer 16, or can be below such elevational level, depending on whether the polishing process has removed any of the material of silicon nitride layer 16. Generally, the polishing process removes some of silicon nitride layer 16, but will slow significantly upon reaching silicon nitride layer 16 such that silicon nitride layer 16 effectively functions as an etch stop layer to define an end point of the polishing process. Exemplary polishing processes include chemical-mechanical polishing, as well as dry and wet etches selective for silicon dioxide relative to silicon nitride. In particular applications, insulative material 40 comprises silicon dioxide and is polished down to a level that is above the upper surface of the silicon nitride. The material 40 is then brought to about level with the upper surface of the silicon nitride with a subsequent wet acid (hydrofluoric acid) dip.
Ideally, upper surface 60 will be substantially planar. However, as shown a problem frequently occurs during the polishing of insulative material 40 wherein concavities 62 occur at the top of isolation regions 50, 52, 54, 56 and 58. Such problem is commonly referred to as “dishing.” The problem is frequently more severe at wider isolation regions, corresponding to wider trenches, (i.e., isolation region 54) than at narrower isolation regions (i.e., isolation regions 50, 52, 56 and 58). The dishing can become particularly pronounced for isolation regions having widths greater than or equal to about 5 microns.
Referring to FIGS. 6 and 7, nitride layer 16 (FIG. 5) is removed, and subsequently pad oxide 14 is stripped. The stripping of pad oxide layer 14 can be accomplished with a hydrofluoric acid dip. Such dip also removes some of the silicon oxide from isolation regions 50, 52, 54, 56, and 58, and accordingly reduces a height of the oxide in such isolation regions.
Referring to FIG. 8, a sacrificial silicon dioxide layer 19 is formed over substrate 12. Such sacrificial silicon dioxide layer can be grown from silicon of substrate 12, or deposited over substrate 12.
Referring to FIG. 9, sacrificial silicon dioxide layer 19 is stripped from over substrate 12. The stripping of sacrificial silicon dioxide layer 19 can be accomplished with a hydrofluoric acid dip. Such dip also removes some of the silicon oxide from isolation regions 50, 52, 54, 56, and 58, and accordingly reduces a height of the oxide in such isolation regions.
Referring to FIG. 10, a gate oxide layer 21 is formed over substrate 12. Such gate oxide layer can be grown from silicon of substrate 12, or deposited over substrate 12. It is noted that only pertinent processing steps are discussed in describing FIGS. 8–10, and that additional processing steps (in addition to those discussed) can occur between the forming of the sacrificial oxide layer and the forming of the gate oxide layer.
As shown in FIG. 10, the dishing described with reference to FIG. 5 can remain in isolation regions 50, 52, 54, 56 and 58 after the processing of FIGS. 6–10, and can result in at least some of the isolation regions having portions below an elevational level of the upper surface of substrate 12. The dishing also causes the isolation regions to have corners 70 which are not right angles. Such corners 70 can undesirably affect operating voltages of devices formed proximate isolation regions 50, 52, 54, 56 and 58, and can, for example, result in non-uniformity of threshold voltages for such devices. It would therefore be desirable to develop alternative methods of forming isolation regions.